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sa8016 2.5ghz low voltage fractional-n synthesizer product specification supersedes data of 1999 apr 16 1999 nov 04 integrated circuits
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 2 1999 nov 04 8532142 22636 general description the sa8016 bicmos device integrates programmable dividers, charge pumps and a phase comparator to implement a phase-locked loop. the device is designed to operate from 3 nicd cells, in pocket phones, with low current and nominal 3 v supplies. the synthesizer operates at vco input frequencies up to 2.5 ghz. the synthesizer has fully programmable main and reference dividers. all divider ratios are supplied via a 3-wire serial programming bus. separate power and ground pins are provided to the analog and digital circuits. the ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. v ddcp must be greater than or equal to v dd . the charge pump current (gain) is set by an external resistance at the r set pin . only passive loop filters could be used; the charge pump operates within a wide voltage compliance range to provide a wider tuning range. features ? low phase noise ? low power ? fully programmable main divider ? internal fractional spurious compensation ? hardware and software power down ? split supply for v dd and v ddcp applications ? 3502500 mhz wireless equipment ? cellular phones (all standards) ? wlan ? portable battery-powered radio equipment. sr01505 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 lock test v dd gnd rfin+ rfin gnd cp php pon strobe data clock refin+ refin r set v ddcp figure 1. tssop16 pin configuration 13 7 2 3 4 5 6 top view 1 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 data clock refin+ refin n/c sr02174 n/c v ddpre gnd gnd pre rfin+ rfin n/c n/c gnd cp php n/c v ddcp r n/c strobe pon lock test v dd set figure 2. hbcc24 pin configuration quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 2.7 e 5.5 v v ddcp analog supply voltage v ddcp v dd 2.7 e 5.5 v i ddcp +i dd total supply current e 8.0 9.5 ma i ddcp +i dd total supply current in power-down mode e 1 e m a f vco input frequency 350 e 2500 mhz f ref crystal reference input frequency 5 e 40 mhz f pc maximum phase comparator frequency e 4 mhz t amb operating ambient temperature 40 e +85 c ordering information type number package type number name description version sa8016dh tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 SA8016WC hbcc24 plastic, heatsink bottom chip carrier; 24 terminals; body 4 4 0.65 mm (csp package) sot564-1
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 3 sr01506 clock data strobe rfin+ rfin ref in+ ref in test load signals address decoder 2bit shift register 22bit shift register control latch latch main divider reference divider latch amp 11 12 6 5 15 14 13 2 phase detector comp pump bias pump current setting gnd 4 7 3 gnd cp v dd r set v ddcp php lock 10 9 8 1 pon 16 figure 3. block diagram (tssop16) tssop16 pin description symbol pin description lock 1 lock detect output test 2 test (should be either grounded or connected to v dd ) v dd 3 digital supply gnd 4 digital ground rfin+ 5 rf input to main divider rfin 6 rf input to main divider gnd cp 7 charge pump ground php 8 main normal charge pump v ddcp 9 charge pump supply voltage r set 10 external resistor from this pin to ground sets the charge pump current refin 11 reference input refin+ 12 reference input clock 13 programming bus clock input data 14 programming bus data input strobe 15 programming bus enable input pon 16 power down control
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 4 hbcc24 pin description symbol pin description v ddpre 1 prescaler supply voltage gnd 2 digital ground gnd pre 3 prescaler ground rfin+ 4 rf input to main divider rfin 5 rf input to main divider n/c 6 not connected n/c 7 not connected gnd cp 8 charge pump ground php 9 main normal charge pump n/c 10 not connected v ddcp 11 charge pump supply voltage r set 12 external resistor from this pin to ground sets the charge pump current n/c 13 not connected n/c 14 not connected refin 15 reference input refin+ 16 reference input clock 17 programming bus clock input data 18 programming bus data input n/c 19 not connected strobe 20 programming bus enable input pon 21 power down control lock 22 lock detect output test 23 test (should be either grounded or connected to v dd ) v dd 24 digital supply note: 1. gnd cp is connected to the die-pad.
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 5 limiting values in accordance with the absolute maximum rating system (iec 134). symbol parameter min. max. unit v dd digital supply voltage 0.3 +5.5 v v ddcp analog supply voltage 0.3 +5.5 v d v ddcp v dd difference in voltage between v ddcp and v dd (v ddcp v dd ) 0.3 +2.8 v v n voltage at pins 1, 2, 5, 6, 11 to 16 0.3 v dd + 0.3 v v 1 voltage at pin 8, 9 0.3 v ddcp + 0.3 v d v gnd difference in voltage between gnd cp and gnd (these pins should be connected together) 0.3 +0.3 v t stg storage temperature 55 +125 c t amb operating ambient temperature 40 +85 c t j maximum junction temperature 150 c handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter value unit r th ja thermal resistance from junction to ambient in free air 120 k/w
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 6 characteristics v ddcp = v dd = +3.0v, t amb = +25 c; unless otherwise specified. symbol parameter conditions min. typ. max. unit supply; pins 3, 9 v dd digital supply voltage 2.7 5.5 v v ddcp analog supply voltage v ddcp = v dd 2.7 5.5 v i ddtotal synthesizer operational total supply current v dd = +3.0 v 8.0 9.5 ma i standby total supply current in power-down mode logic levels 0 or v dd 1 m a rfin main divider input; pins 5, 6 f vco vco input frequency 350 2500 mhz v rfin(rms) ac-coupled input signal level r in (external) = r s = 50 w ; single-ended drive; max. limit is indicative @ 500 to 2500 mhz 18 0 dbm z irfin input impedance (real part) f vco = 2.4 ghz 210 w c irfin typical pin input capacitance f vco = 2.4 ghz 1.0 pf n main main divider ratio 512 65535 f pcmax maximum loop comparison frequency indicative, not tested 4 mhz reference divider input; pins 11, 12 f refin input frequency range from tcxo 5 40 mhz vrfin ac-coupled input signal level single-ended drive; max. limit is indicative 360 1300 mv pp z refin input impedance (real part) f ref = 20 mhz 10 k w c refin typical pin input capacitance f ref = 20 mhz 1.0 pf r ref reference division ratio 4 1023 charge pump current setting resistor input; pin 10 r set external resistor from pin to ground 6 7.5 15 k w v set regulated voltage at pin r set =7.5 k w 1.25 v charge pump outputs (including fractional compensation pump); pin 8; r set =7.5k w , fc=80 i cp charge pump current ratio to i set 1 current gain i ph /i set 15 +15 % i match sink-to-source current matching v ph =1/2 v ddcp 10 +10 % i zout output current variation versus v ph 2 v ph in compliance range 10 +10 % i lph charge pump off leakage current v ph =1/2 v cc 10 +10 na v ph charge pump voltage compliance 0.7 v ddcp 0.8 v
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 7 symbol unit max. typ. min. conditions parameter phase noise (r set = 7.5 k w , cp = 00) synthesizer's contribution to close-in phase noise of 900 mhz rf signal at 1 khz offset. gsm f ref = 13mhz, tcxo, 90 dbc/hz synthesizer's contribution to close-in phase noise of 1800 mhz rf signal at 1 khz offset. f ref = 13mhz , tcxo , f comp = 1mhz indicative, not tested 83 dbc/hz (f) synthesizer's contribution to close-in phase noise of 800 mhz rf signal at 1 khz offset. tdma f ref = 19.44mhz, tcxo, 85 dbc/hz synthesizer's contribution to close-in phase noise of 2100 mhz rf signal at 1 khz offset. f ref = 19 . 44mhz , tcxo , f comp = 240khz indicative, not tested 77 dbc/hz interface logic input signal levels; pins 13, 14, 15, 16 v ih high level input voltage 0.7*v dd v dd +0.3 v v il low level input voltage 0.3 0.3*v dd v i leak input leakage current logic 1 or logic 0 0.5 +0.5 m a lock detect output signal (in push/pull mode); pin 1 v ol low level output voltage i sink = 2ma 0.4 v v oh high level output voltage i source = 2ma v dd 0.4 v notes: 1. i set = v set r set bias current for charge pumps. 2. the relative output current variation is defined as: i out i out 2 . (i 2 i 1 ) i(i 2 i 1 )i ; with v 1 0.7v, v 2 v ddcp 0.8v (see figure 4.) i 2 i 1 i 2 i 1 v 1 v 2 current v ph sr00602 i zout figure 4. relative output current variation
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 8 functional description main fractional-n divider the rfin inputs drive a pre-amplifier to provide the clock to the first divider stage. for single ended operation, the signal should be fed to one of the inputs while the other one is ac grounded. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from 18 dbm to 0 dbm, and at frequencies as high as 2.5 ghz. the divider consists of a fully programmable bipolar prescaler followed by a cmos counter. total divide ratios range from 512 to 65536. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also, the fractional accumulator is incremented by the value of nf. the accumulator works with modulo q set by fmod. when the accumulator overflows, the overall division ratio n will be increased by 1 to n + 1, the average division ratio over q main divider cycles (either 5 or 8) will be nfrac n nf q the output of the main divider will be modulated with a fractional phase ripple. the phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. the reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance. reference divider the reference divider consists of a divider with programmable values between 4 and 1023 followed by a three bit binary counter. the 3 bit sm (sa) register (see figure 5) determines which of the 5 output pulses are selected as the main (auxiliary) phase detector input. phase detector (see figure 6) the reference and main (aux) divider outputs are connected to a phase/frequency detector that controls the charge pump. the pump current is set by an external resistor in conjunction with control bits cp0 and cp1 in the b-word (see charge pump table). the dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps on for a minimum time at every cycle (backlash time) providing improved linearity. sr01415 divide by r /2 /2 /2 /2 reference input sm=o000o sm=o001o sm=o010o sm=o011o sm=o100o sa=o100o sa=o011o sa=o010o sa=o001o sa=o000o to main phase detector to auxiliary phase detector figure 5. reference divider
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 9 sr01451 r x p n ref divider aux/main divider d q clk a1o r d r clk a1o x q n p t v cc i ph gnd ptype charge pump ntype charge pump r f ref f ref i ph t t figure 6. phase detector structure with timing
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 10 main output charge pumps and fractional compensation currents (see figure 7) the main charge pumps on pins php and phi are driven by the main phase detector and the charge pump current values are determined by the current at pin r set in conjunction with bits cp0, cp1 in the b-word (see table of charge pump ratios). the fractional compensation is derived from the current at r set , the contents of the fractional accumulator frd and by the program value of the fdac. the timing for the fractional compensation is derived from the main divider. the main charge pumps will enter speed up mode after the a-word is set and strobe goes high. when strobe goes low, charge pump will exit speed up mode. principle of fractional compensation the fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. if i comp is the compensation current and i pump is the pump current, then for each charge pump: i pump_total = i pump + i comp . the compensation is done by sourcing a small current, i comp , see figure 8, that is proportional to the fractional error phase. for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. the width of the fractional compensation pulse is fixed to 128 vco cycles, the amplitude is proportional to the fractional accumulator value and is adjusted by fdac values (bits fc70 in the b-word). the fractional compensation current is derived from the main charge pump in that it follows all the current scaling through external resistor setting, r set , programming or speed-up operation. for a given charge pump, i comp = ( i pump / 128 ) * ( fdac / 5*128) * frd frd is the fractional accumulator value. the target values for fdac are: 128 for fmod = 1 (modulo 5) and 80 for fmod = 0 (modulo 8). sr01416 reference r main m divide ratio detector output accumulator fractional compensation current output on pump n n n+1 n n+1 241 3 0 pulse width modulation pulse level modulation ma m a note: for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the ch arge pump ripple output. figure 7. waveforms for nf = 2 modulo 5 fraction = 2 / 5 sr01682 f rf 1930.140 mhz main divider n = 8042 fractional accumulator f ref 240 khz 240.016 khz i comp i pump loop filter & vco fmod nf figure 8. current injection concept
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 11 charge pump currents cp0 i php i phpsu 0 3xi set 15xl set 1 1xl set 5xl set notes: 1. i set =v set /r set bias current for charge pumps. 2. i phpsu is the total current at pin php during speed up condition. lock detect the output lock maintains a logic `1' when the auxiliary phase detector anded with the main phase detector indicates a lock condition. the lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than 1 period of the frequency at the input refin+, . one counter can fulfill the lock condition when the other counter is powered down. out of lock (logic `0') is indicated when both counters are powered down. power-down mode the power-down signal can be either hardware (pon) or software (pd). the pon signal is exclusively ored with the pd bits in b-word. if pon = 0, then the part is powered up when pd = 1. pon can be used to invert the polarity of the software bit pd. when the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 12 serial programming bus the serial input is a 3-wire input (clock, strobe, data) to program all counter divide ratios, fractional compensation dac, selection and enable bits. the programming data is structured into 24 bit words; each word includes 2 or 3 address bits. figure 9 shows the timing diagram of the serial input. when the strobe goes active high, the clock is disabled and the data in the shift register remains unchanged. depending on the address bits, the data is latched into different working registers or temporary registers. in order to fully program the synthesizer, 2 words must be sent: b, and a. table 1 shows the format and the contents of each word. the d word is normally used for testing purposes. when sending the b-word, data bits fc70 for the fractional compensation dac are not loaded immediately. instead they are stored in temporary registers. only when the a-word is loaded, these temporary registers are loaded together with the main divider ratio. serial bus timing characteristics (see figure 9) v dd = v ddcp =+3.0v; t amb = +25 c unless otherwise specified. symbol parameter min. typ. max. unit serial programming clock; clk t r input rise time 10 40 ns t f input fall time 10 40 ns t cy clock period 100 ns enable programming; strobe t start delay to rising clock edge 40 ns t w minimum inactive pulse width 1/f comp ns t su;e enable set-up time to next clock edge 20 ns register serial input data; data t su;dat input data to clock set-up time 20 ns t hd;dat input data to clock hold time 20 ns application information sr01417 clk data strobe address lsb t su;dat t hd;dat t r t w t f t su;e t start t cy msb figure 9. serial bus timing diagram
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 13 data format table 1. format of programmed data last in msb serial programming format first in lsb p23 p22 p21 p20 ../.. ../.. p1 p0 table 2. a word, length 24 bits last in msb lsb first in address fmod fractional-n main divider ratio spare 0 0 fm nf2 nf1 nf0 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 sp1 sp2 default: 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 a word select fixed to 00. fractional modulus select fm 0 = modulo 8, 1 = modulo 5. fractional-n increment nf2..0 fractional n increment values 000 to 111. n-divider n0..n15, main divider values 512 to 65535 allowed for divider ratio. table 3. b word, length 24 bits address reference divider lock pd cp fractional compensation dac spare 0 1 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 lo main cp0 fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 sp3 default: 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 b word select fixed to 01 r-divider r0..r9, reference divider values 4 to 1023 allowed for divider ration. charge pump current ratio cp0: charge pump current ratio, see table of charge pump currents. lock detect output l0 0 main lock detect signal present at the lock pin (push/pull). 1 main lock detect signal present at the lock pin (open drain). when main loop is in power down mode, the lock indicator is low. power down main = 1: power to main divider, reference divider, main charge pumps, main = 0 to power down. fractional compensation fc7..0 fractional compensation charge pump current dac, values 0 to 255. table 4. d word, length 24 bits address synthesizer test bits synthesizer test bits 1 1 0 tspu default: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tspu: speed up = 1 forces the main charge pumps in speed-up mode all the time. note : all test bits must be set to 0 for normal operation.
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 14 sr01911 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 800 600 400 200 0 200 400 600 800 icp (ua) compliance voltage (v) i set = 206.67 a i set = 165.33 a i set = 103.33 a i set = 51.67 a i set = 51.67 a i set = 103.33 a i set = 165.33 a i set = 206.67 a figure 10. php charge pump output vs. i set (cp = 0, temp = 25 c) sr01912 600 400 200 0 200 400 600 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 compliance voltage (v) icp (ua) temp = 85 c temp = 25 c temp = 40 c v dd = 3.0 v i set = 165.33 m a figure 11. php charge pump output vs. temperature (cp = 0; v dd = 3.0 v; i set = 165.33 a) sr01913 icp (ua) 250 250 200 150 100 50 0 50 100 150 200 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 compliance voltage (v) i set = 206.67 a i set = 165.33 a i set = 103.33 a i set = 51.67 a i set = 51.67 a i set = 103.33 a i set = 165.33 a i set = 206.67 a figure 12. php charge pump output vs. i set (cp = 1; temp = 25 c) sr01914 200 icp (ua) 200 150 100 50 0 50 100 150 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 compliance voltage (v) temp = 85 c temp = 25 c temp = 40 c v dd = 3.0 v i set = 165.33 m a figure 13. php charge pump output vs. temperature (cp = 1; v dd = 3.0 v; i set = 165.33 a) sr01915 3500 icp (ua) 2500 1500 500 0 500 1500 2500 3500 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 compliance voltage (v) i set = 206.67 a i set = 165.33 a i set = 103.33 a i set = 51.67 a i set = 51.67 a i set = 103.33 a i set = 165.33 a i set = 206.67 a figure 14. phpsu charge pump output vs. i set (cp = 0; temp = 25 c) sr01916 3000 icp (ua) 2000 1000 0 1000 2000 3000 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 compliance voltage (v) temp = 85 c temp = 25 c temp = 40 c figure 15. phpsu charge pump output vs. temperature (cp = 0; v dd = 3.0 v; i set = 165.33 a)
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 15 i set = 165.33 a i set = 206.67 a sr01917 icp (ua) i set = 206.67 a i set = 165.33 a i set = 103.33 a i set = 51.67 a i set = 51.67 a i set = 103.33 a 1500 1000 500 0 500 1000 1500 0 0.25 0.5 0.75 1 1.5 1.25 1.75 2 2.25 2.5 2.75 3 compliance voltage (v) figure 16. phpsu charge pump output vs. i set (cp = 1; temp = 25 c) sr01918 1000 icp (ua) 1000 800 600 400 200 0 200 400 600 800 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 compliance voltage (v) temp = 85 c temp = 25 c temp = 40 c figure 17. phpsu charge pump output vs. temperature (cp = 1; v dd = 3.0 v; i set = 165.33 a) sr01919 40 minimum signal input level (dbm) v dd = 5.00 v v dd = 3.75 v v dd = 3.00 v v dd = 2.70 v 35 30 25 20 15 10 5 0 1300 1500 1700 1900 2100 2300 2500 2700 2900 frequency (mhz) figure 18. main divider input sensitivity vs. frequency and supply voltage (temp = 25 c) sr01920 45 minimum signal input level (dbm) temp = +85 c temp = +25 c temp = 40 c 40 35 30 25 20 15 10 0 5 1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 frequency (mhz) figure 19. main divider input sensitivity vs. frequency and temperature (v dd = 3.00 v) sr01921 minimum signal power level (dbm) 55 50 45 40 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 frequency (mhz) v dd = 5.00 v v dd = 3.75 v v dd = 3.00 v v dd = 2.70 v figure 20. reference divider input sensitivity vs. frequency and supply voltage (temp = 25 c) sr01922 55 minimum signal power level (dbm) 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 frequency (mhz) temp = +85 c temp = +25 c temp = 40 c figure 21. reference divider input sensitivity vs. frequency and temperature (v dd = 3.00 v)
philips semiconductors product specification sa8016 2.5ghz low voltage fractional-n synthesizer 1999 nov 04 16 sr01923 10.5 i total (ma) 11 10 9.5 9 8.5 8 7.5 2 2.5 3 3.5 4 4.5 5 5.5 6 temp = +85 c temp = +25 c temp = 40 c supply voltage (v) figure 22. current supply over v dd
2.5ghz low voltage fractional-n frequency synthesizer philips semiconductors product specification sa8016 1999 nov 04 17 hbcc24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm sot564-1
2.5ghz low voltage fractional-n frequency synthesizer philips semiconductors product specification sa8016 1999 nov 04 18 tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1
2.5ghz low voltage fractional-n frequency synthesizer philips semiconductors product specification sa8016 1999 nov 04 19 notes
2.5ghz low voltage fractional-n frequency synthesizer philips semiconductors product specification sa8016 1999 nov 04 20 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 11-99 document order number: 9397 750 06564

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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